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» Reducing Power in High-Performance Microprocessors
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ICRA
2007
IEEE
160views Robotics» more  ICRA 2007»
15 years 4 months ago
Morphing Bus: A rapid deployment computing architecture for high performance, resource-constrained robots
— For certain applications, field robotic systems require small size for cost, weight, access, stealth or other reasons. Small size results in constraints on critical resources s...
Colin D'Souza, Byung Hwa Kim, Richard M. Voyles
77
Voted
IEEEINTERACT
2003
IEEE
15 years 2 months ago
High Performance Code Generation through Lazy Activation Records
For call intensive programs, function calls are major bottlenecks during program execution since they usually force register contents to be spilled into memory. Such register to m...
Manoranjan Satpathy, Rabi N. Mahapatra, Siddharth ...
ISPAN
2000
IEEE
15 years 2 months ago
Versatile Processor Design for Efficiency and High Performance
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...
Sotirios G. Ziavras
MICRO
1999
IEEE
102views Hardware» more  MICRO 1999»
15 years 1 months ago
Evaluation of a High Performance Code Compression Method
Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been propos...
Charles Lefurgy, Eva Piccininni, Trevor N. Mudge
81
Voted
ICETET
2009
IEEE
14 years 7 months ago
High Performance WDM Using Semiconductor Tunable Laser
Advances in optical networking have lead to the explosive growth of communication network. Telecom applications began to drive significant investments into this field to support t...
S. S. Agrawal, K. D. Kulat, M. B. Daigavane