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» Reducing Power in High-Performance Microprocessors
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MICRO
2006
IEEE
144views Hardware» more  MICRO 2006»
15 years 3 months ago
Die Stacking (3D) Microarchitecture
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...
Bryan Black, Murali Annavaram, Ned Brekelbaum, Joh...
WCE
2007
14 years 10 months ago
VHDL Implementation of Multiplierless, High Performance DWT Filter Bank
—The JPEG 2000 image coding standard employs the biorthogonal 9/7 wavelet for lossy compression. The performance of hardware implementation of 9/7-filter bank depends on accuracy...
M. M. Aswale, R. B. Patil
ICONS
2009
IEEE
15 years 4 months ago
Power Saving of Real Time Embedded Sensor for Medical Remote Monitoring
The power saving is one of the important issue in the embedded systems. To reduce the consumption of the microprocessor of such a system, a way is to power down it when it is inac...
Frederic Fauberteau, Serge Midonnet, Dan Istrate
PPSC
1997
14 years 11 months ago
High-Performance Object-Oriented Scientific Programming in Fortran 90
We illustrate how Fortran 90 supports object-oriented concepts by example of plasma particle computations on the IBM SP. Our experience shows that Fortran 90 and object-oriented m...
Charles D. Norton, Viktor K. Decyk, Boleslaw K. Sz...
ISVLSI
2008
IEEE
143views VLSI» more  ISVLSI 2008»
15 years 4 months ago
BTB Access Filtering: A Low Energy and High Performance Design
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras