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» Reducing Power in High-Performance Microprocessors
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83
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ISLPED
2005
ACM
110views Hardware» more  ISLPED 2005»
15 years 3 months ago
Complexity reduction in an nRERL microprocessor
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
Seokkee Kim, Soo-Ik Chae
DAC
2004
ACM
15 years 10 months ago
Design optimizations for microprocessors at low temperature
We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refrigeration with...
Arman Vassighi, Ali Keshavarzi, Siva Narendra, Ger...
HPCA
2011
IEEE
14 years 1 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
89
Voted
ICCD
2004
IEEE
131views Hardware» more  ICCD 2004»
15 years 6 months ago
3D Processing Technology and Its Impact on iA32 Microprocessors
This short paper explores an implementation of a new technology called 3D die stacking and describes research activity at Intel. 3D die stacking is the bonding of two die either f...
Bryan Black, Donald Nelson, Clair Webb, Nick Samra
ISQED
2005
IEEE
78views Hardware» more  ISQED 2005»
15 years 3 months ago
Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems
— Multiple power supply voltages are often used in modern high performance ICs such as microprocessors to decrease power consumption without affecting circuit speed. The system o...
Mikhail Popovich, Eby G. Friedman