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» Reducing Power in High-Performance Microprocessors
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CASES
2006
ACM
15 years 1 months ago
Cost-efficient soft error protection for embedded microprocessors
Device scaling trends dramatically increase the susceptibility of microprocessors to soft errors. Further, mounting demand for embedded microprocessors in a wide array of safety c...
Jason A. Blome, Shantanu Gupta, Shuguang Feng, Sco...
DFT
2003
IEEE
142views VLSI» more  DFT 2003»
15 years 3 months ago
Exploiting Instruction Redundancy for Transient Fault Tolerance
This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller...
Toshinori Sato
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
15 years 3 months ago
A non-uniform cache architecture for low power system design
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
Tohru Ishihara, Farzan Fallah
DAC
2000
ACM
15 years 2 months ago
Macro-driven circuit design methodology for high-performance datapaths
Datapath design is one of the most critical elements in the design of a high performance microprocessor. However datapath design is typically done manually, and is often custom st...
Mahadevamurty Nemani, Vivek Tiwari
TOCS
1998
83views more  TOCS 1998»
14 years 9 months ago
Using Value Prediction to Increase the Power of Speculative Execution Hardware
This paper presents an experimental and analytical study of value prediction and its impact on speculative execution in superscalar microprocessors. Value prediction is a new para...
Freddy Gabbay, Avi Mendelson