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» Reducing Power in High-Performance Microprocessors
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DAC
2008
ACM
15 years 10 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...
SAFECOMP
2007
Springer
15 years 3 months ago
Software Encoded Processing: Building Dependable Systems with Commodity Hardware
In future, the decreasing feature size and the reduced power supply will make it much more difficult to built reliable microprocessors. Economic pressure will most likely result in...
Ute Wappler, Christof Fetzer
DATE
2009
IEEE
131views Hardware» more  DATE 2009»
15 years 4 months ago
An event-guided approach to reducing voltage noise in processors
Abstract—Supply voltage fluctuations that result from inductive noise are increasingly troublesome in modern microprocessors. A voltage “emergency”, i.e., a swing beyond tol...
Meeta Sharma Gupta, Vijay Janapa Reddi, Glenn H. H...
ISCA
2010
IEEE
413views Hardware» more  ISCA 2010»
15 years 2 months ago
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations...
Xiaochen Guo, Engin Ipek, Tolga Soyata
ICCD
2005
IEEE
100views Hardware» more  ICCD 2005»
15 years 6 months ago
Power-Efficient Wakeup Tag Broadcast
The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The d...
Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomare...