287 search results - page 28 / 58 » Reducing Power in High-Performance Microprocessors |
ARITH
2001
IEEE
15 years 1 months ago
2001
IEEE
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
104
Voted
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
83
Voted
EUC
2004
Springer
15 years 3 months ago
2004
Springer
Abstract. Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltag...
100
Voted
DAC
2008
ACM
14 years 11 months ago
2008
ACM
The performance advantages in parallel ring-based VCOs are explored. When the number of VCOs is doubled, the parallel VCOs enhance phase noise by 3dB, and the within-chip process-...
EUROMICRO
1998
IEEE
15 years 1 months ago
1998
IEEE
As commodity microprocessors and networks reach performance levels comparable to those used in massively parallel processors, clusters of symmetric multiprocessors are starting to...