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» Reducing Power in High-Performance Microprocessors
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ERSA
2008
145views Hardware» more  ERSA 2008»
14 years 11 months ago
Multicore Devices: A New Generation of Reconfigurable Architectures
For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. Reconfigurable computing systems have demonstrated the low c...
Steven A. Guccione
PATMOS
2007
Springer
15 years 3 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
TCAD
2008
172views more  TCAD 2008»
14 years 9 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
DAC
2005
ACM
14 years 11 months ago
Keeping hot chips cool
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
Ruchir Puri, Leon Stok, Subhrajit Bhattacharya
62
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ASPLOS
2004
ACM
15 years 3 months ago
Scalable selective re-execution for EDGE architectures
Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can r...
Rajagopalan Desikan, Simha Sethumadhavan, Doug Bur...