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» Reducing Power in High-Performance Microprocessors
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OSDI
2000
ACM
14 years 11 months ago
Policies for Dynamic Clock Scheduling
Pocket computers are beginning to emerge that provide sufficient processing capability and memory capacity to run traditional desktop applications and operating systems on them. T...
Dirk Grunwald, Philip Levis, Keith I. Farkas, Char...
MICRO
2000
IEEE
88views Hardware» more  MICRO 2000»
14 years 9 months ago
Two-level hierarchical register file organization for VLIW processors
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
Javier Zalamea, Josep Llosa, Eduard Ayguadé...
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
14 years 9 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
CORR
2010
Springer
89views Education» more  CORR 2010»
14 years 9 months ago
Power optimized programmable embedded controller
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functio...
M. Kamaraju, K. Lal Kishore, A. V. N. Tilak
ISCA
2008
IEEE
105views Hardware» more  ISCA 2008»
15 years 4 months ago
Intra-disk Parallelism: An Idea Whose Time Has Come
Server storage systems use a large number of disks to achieve high performance, thereby consuming a significant amount of power. In this paper, we propose to significantly reduc...
Sriram Sankar, Sudhanva Gurumurthi, Mircea R. Stan