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» Reducing Power in High-Performance Microprocessors
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85
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ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
14 years 8 months ago
Evolution of thread-level parallelism in desktop applications
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
CORR
2010
Springer
177views Education» more  CORR 2010»
14 years 7 months ago
Dynamic Scheduling of Skippable Periodic Tasks with Energy Efficiency in Weakly Hard Real-Time System
Energy consumption is a critical design issue in real-time systems, especially in battery- operated systems. Maintaining high performance, while extending the battery life between...
Santhi Baskaran, P. Thambidurai
IPPS
2008
IEEE
15 years 4 months ago
Low power/area branch prediction using complementary branch predictors
Although high branch prediction accuracy is necessary for high performance, it typically comes at the cost of larger predictor tables and/or more complex prediction algorithms. Un...
Resit Sendag, Joshua J. Yi, Peng-fei Chuang, David...
98
Voted
HPCA
2006
IEEE
15 years 10 months ago
Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads
With the continuing growth in the amount of genetic data, members of the bioinformatics community are developing a variety of data-mining applications to understand the data and d...
Aamer Jaleel, Matthew Mattina, Bruce L. Jacob
ICS
1998
Tsinghua U.
15 years 1 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...