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» Reducing Power in High-Performance Microprocessors
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DAC
2005
ACM
15 years 10 months ago
MP core: algorithm and design techniques for efficient channel estimation in wireless applications
Channel estimation and multiuser detection are enabling technologies for future generations of wireless applications. However, sophisticated algorithms are required for accurate c...
Yan Meng, Andrew P. Brown, Ronald A. Iltis, Timoth...
ICCAD
2010
IEEE
186views Hardware» more  ICCAD 2010»
14 years 7 months ago
Application-Aware diagnosis of runtime hardware faults
Extreme technology scaling in silicon devices drastically affects reliability, particularly because of runtime failures induced by transistor wearout. Currently available online t...
Andrea Pellegrini, Valeria Bertacco
95
Voted
DAC
2010
ACM
14 years 7 months ago
Non-uniform clock mesh optimization with linear programming buffer insertion
Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. Ho...
Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis
ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
15 years 6 months ago
New decompilation techniques for binary-level co-processor generation
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
Greg Stiff, Frank Vahid
76
Voted
JAL
2008
89views more  JAL 2008»
14 years 9 months ago
Experimenting with parallelism for the instantiation of ASP programs
Abstract. In the last few years, the microprocessors technologies have been definitely moving to multi-core architectures, in order to improve performances as well as reduce power ...
Francesco Calimeri, Simona Perri, Francesco Ricca