Sciweavers

287 search results - page 48 / 58
» Reducing Power in High-Performance Microprocessors
Sort
View
MICRO
1996
IEEE
96views Hardware» more  MICRO 1996»
15 years 1 months ago
Exceeding the Dataflow Limit via Value Prediction
For decades, the serialization constraints imposed by true data dependences have been regarded as an absolute limit--the dataflow limit--on the parallel execution of serial progra...
Mikko H. Lipasti, John Paul Shen
TC
2010
14 years 4 months ago
A Counter Architecture for Online DVFS Profitability Estimation
Dynamic voltage and frequency scaling (DVFS) is a well known and effective technique for reducing power consumption in modern microprocessors. An important concern though is to est...
Stijn Eyerman, Lieven Eeckhout
OSDI
2002
ACM
15 years 10 months ago
Vertigo: Automatic Performance-Setting for Linux
Combining high performance with low power consumption is becoming one of the primary objectives of processor designs. Instead of relying just on sleep mode for conserving power, a...
Krisztián Flautner, Trevor N. Mudge
WAN
1998
Springer
15 years 1 months ago
The NRW Metacomputing Initiative
In this paper the Northrhine-Westphalian metacomputing initiative is described. We start by discussing various general aspects of metacomputing and explain the reasons for founding...
Uwe Schwiegelshohn, Ramin Yahyapour
ISQED
2007
IEEE
136views Hardware» more  ISQED 2007»
15 years 4 months ago
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...
Rajani Kuchipudi, Hamid Mahmoodi