287 search results - page 49 / 58 » Reducing Power in High-Performance Microprocessors |
PDP
2010
IEEE
15 years 2 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
72
Voted
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
101
click to vote
ISLPED
2009
ACM
15 years 4 months ago
2009
ACM
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
70
Voted
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
The Software-Defined Radio (SDR) concept aims to enabling costeffective multi-mode baseband solutions for wireless terminals. However, the growing complexity of new communication ...
ICPADS
2007
IEEE
15 years 4 months ago
2007
IEEE
- Due to the increasing complexity of scientific models, large-scale simulation tools often require a critical amount of computational power to produce results in a reasonable amou...