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» Reducing Power in High-Performance Microprocessors
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ISPASS
2008
IEEE
15 years 4 months ago
Dynamic Thermal Management through Task Scheduling
The evolution of microprocessors has been hindered by their increasing power consumption and the heat generation speed on-die. High temperature impairs the processor’s reliabili...
Jun Yang 0002, Xiuyi Zhou, Marek Chrobak, Youtao Z...
89
Voted
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
15 years 4 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
74
Voted
CLUSTER
2009
IEEE
15 years 4 months ago
Power-aware scheduling of virtual machines in DVFS-enabled clusters
—With the advent of Cloud computing, large-scale virtualized compute and data centers are becoming common in the computing industry. These distributed systems leverage commodity ...
Gregor von Laszewski, Lizhe Wang, Andrew J. Younge...
MICRO
2009
IEEE
129views Hardware» more  MICRO 2009»
15 years 4 months ago
In-network coherence filtering: snoopy coherence without broadcasts
With transistor miniaturization leading to an abundance of on-chip resources and uniprocessor designs providing diminishing returns, the industry has moved beyond single-core micr...
Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha
FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
15 years 3 months ago
A Field Programmable RFID Tag and Associated Design Flow
Current Radio Frequency Identification (RFID) systems generally have long design times and low tolerance to changes in specification. This paper describes a field programmable,...
Alex K. Jones, Raymond R. Hoare, Swapna R. Donthar...