287 search results - page 56 / 58 » Reducing Power in High-Performance Microprocessors |
ICNP
2007
IEEE
14 years 17 days ago
2007
IEEE
—Data structures representing directed graphs with edges labeled by symbols from a finite alphabet are used to implement packet processing algorithms used in a variety of network...
ICS
2005
Tsinghua U.
13 years 11 months ago
2005
Tsinghua U.
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
DAC
2002
ACM
14 years 7 months ago
2002
ACM
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
PPOPP
2009
ACM
14 years 6 months ago
2009
ACM
Due to power wall, memory wall, and ILP wall, we are facing the end of ever increasing single-threaded performance. For this reason, multicore and manycore processors are arising ...
CASES
2006
ACM
14 years 7 days ago
2006
ACM
With advances in process technology, soft errors (SE) are becoming an increasingly critical design concern. Due to their large area and high density, caches are worst hit by soft ...