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» Reducing Power in High-Performance Microprocessors
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PVLDB
2010
204views more  PVLDB 2010»
14 years 8 months ago
Cheetah: A High Performance, Custom Data Warehouse on Top of MapReduce
Large-scale data analysis has become increasingly important for many enterprises. Recently, a new distributed computing paradigm, called MapReduce, and its open source implementat...
Songting Chen
ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
15 years 1 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
ICCD
2002
IEEE
110views Hardware» more  ICCD 2002»
15 years 6 months ago
Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors
We introduce Branch Predictor Prediction (BPP) as a power-aware branch prediction technique for high performance processors. Our predictor reduces branch prediction power dissipat...
Amirali Baniasadi, Andreas Moshovos
CLUSTER
2005
IEEE
15 years 3 months ago
A Feasibility Analysis of Power Awareness in Commodity-Based High-Performance Clusters
We present a feasibility study of a power-reduction scheme that reduces the thermal power of processors by lowering frequency and voltage in the context of high-performance comput...
Chung-Hsing Hsu, Wu-chun Feng
66
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DSD
2004
IEEE
104views Hardware» more  DSD 2004»
15 years 1 months ago
A Static Low-Power, High-Performance 32-bit Carry Skip Adder
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
Kai Chirca, Michael J. Schulte, John Glossner, Hao...