Sciweavers

93 search results - page 18 / 19
» Reducing Processor Power Consumption by Improving Processor ...
Sort
View
LCTRTS
2007
Springer
14 years 15 days ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
TVLSI
2010
13 years 1 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
WCE
2007
13 years 7 months ago
Data Communication and Parallel Computing on Twisted Hypercubes
Massively parallel distributed-memory architectures are receiving increasing attention to meet the increasing demand on processing power. Many topologies have been proposed for int...
Emad Abuelrub
STORAGESS
2005
ACM
13 years 12 months ago
Expecting the unexpected: adaptation for predictive energy conservation
The use of access predictors to improve storage device performance has been investigated for both improving access times, as well as a means of reducing energy consumed by the dis...
Jeffrey P. Rybczynski, Darrell D. E. Long, Ahmed A...
ISLPED
2005
ACM
93views Hardware» more  ISLPED 2005»
13 years 12 months ago
Power-aware code scheduling for clusters of active disks
In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called Cluster of Active Disks (CAD), where the storag...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir