253 search results - page 10 / 51 » Reducing SoC Simulation and Development Time |
TOG
2008
14 years 9 months ago
2008
We present a new discretization for the physics-based animation of developable surfaces. Constrained to not deform at all in-plane but free to bend out-of-plane, these are an exce...
ISCAS
2007
IEEE
15 years 3 months ago
2007
IEEE
— Mismatches between sample-and-hold (S/H) circuits in a time-interleaved analog-to-digital data converter (ADC) cause undesirable distortions in the output spectrum. To reduce t...
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DSRT
2008
IEEE
14 years 11 months ago
2008
IEEE
The complexity and the variety of the deployed timedependent systems, as well as the high degree of reliability required for their global functioning, justify the care provided to...
DFT
1999
IEEE
15 years 1 months ago
1999
IEEE
In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some wellknown memory ...
PADS
2005
ACM
15 years 3 months ago
2005
ACM
Simulation of large-scale networks requires enormous amounts of memory and processing time. One way of speeding up these simulations is to distribute the model over a number of co...