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» Reducing Synchronization Overhead in Parallel Simulation
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ICPP
1995
IEEE
15 years 1 months ago
Impact of Load Imbalance on the Design of Software Barriers
Software barriers have been designed and evaluated for barrier synchronization in large-scale shared-memory multiprocessors, under the assumption that all processorsreach the sync...
Alexandre E. Eichenberger, Santosh G. Abraham
66
Voted
VTC
2006
IEEE
107views Communications» more  VTC 2006»
15 years 3 months ago
Multi-Ring Cyclic Scheduling for Spatial-TDMA Energy-Saving MAC Protocol in MANET
—this paper presents an energy-saving Multi-Ring Cyclic Scheduling for Spatial-TDMA (MRSTDMA). We design a cyclic scheduling of STDMA to realize the energy-saving property of STD...
Wei-Chih Harry Lin, Shuoh-Ren Tsai
PPOPP
2009
ACM
15 years 10 months ago
An efficient transactional memory algorithm for computing minimum spanning forest of sparse graphs
Due to power wall, memory wall, and ILP wall, we are facing the end of ever increasing single-threaded performance. For this reason, multicore and manycore processors are arising ...
Seunghwa Kang, David A. Bader
ASPLOS
2010
ACM
15 years 29 days ago
Butterfly analysis: adapting dataflow analysis to dynamic parallel monitoring
Online program monitoring is an effective technique for detecting bugs and security attacks in running applications. Extending these tools to monitor parallel programs is challeng...
Michelle L. Goodstein, Evangelos Vlachos, Shimin C...
ICCD
2006
IEEE
97views Hardware» more  ICCD 2006»
15 years 6 months ago
Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...
Jin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, Sa...