175 search results - page 7 / 35 » Reducing Synchronization Overhead in Parallel Simulation |
IPPS
2000
IEEE
15 years 2 months ago
2000
IEEE
Parallel simulation techniques are often employed to meet the computational requirements of large hardware simulations in order to reduce simulation time. In addition, partitionin...
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DAC
2004
ACM
15 years 1 months ago
2004
ACM
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
ICS
2009
Tsinghua U.
15 years 4 months ago
2009
Tsinghua U.
Ethernet line rates are projected to reach 100 Gbits/s by as soon as 2010. While in principle suitable for high performance clustered and parallel applications, Ethernet requires ...
CODES
2003
IEEE
15 years 2 months ago
2003
IEEE
Hardware/Software cosimulation is the key process to shorten the design turn around time. We have proposed a novel technique, called virtual synchronization, for fast and time acc...
CASES
2007
ACM
15 years 1 months ago
2007
ACM
Advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Efficient utilization of...