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» Reducing cache misses through programmable decoders
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ICCD
2004
IEEE
149views Hardware» more  ICCD 2004»
15 years 8 months ago
Adaptive Selection of an Index in a Texture Cache
For a specified application, there is an opportunity to improve cache performance by smart choosing of index bits of a cache. A texture cache for texture mapping of 3D computer gr...
Chun-Ho Kim, Lee-Sup Kim
ICCD
2008
IEEE
118views Hardware» more  ICCD 2008»
15 years 8 months ago
Adaptive techniques for leakage power management in L2 cache peripheral circuits
— Recent studies indicate that a considerable amount of an L2 cache leakage power is dissipated in its peripheral circuits, e.g., decoders, word-lines and I/O drivers. In additio...
Houman Homayoun, Alexander V. Veidenbaum, Jean-Luc...
105
Voted
ISCA
2006
IEEE
182views Hardware» more  ISCA 2006»
15 years 5 months ago
Cooperative Caching for Chip Multiprocessors
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...
Jichuan Chang, Gurindar S. Sohi
SC
1991
ACM
15 years 3 months ago
Delayed consistency and its effects on the miss rate of parallel programs
In cache based multiprocessors a protocol must maintain coherence among replicated copies of shared writable data. In delayed consistency protocols the effect of out-going and in-...
Michel Dubois, Jin-Chin Wang, Luiz André Ba...
110
Voted
CGO
2004
IEEE
15 years 3 months ago
Exploring Code Cache Eviction Granularities in Dynamic Optimization Systems
Dynamic optimization systems store optimized or translated code in a software-managed code cache in order to maximize reuse of transformed code. Code caches store superblocks that...
Kim M. Hazelwood, James E. Smith