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» Reducing energy and delay using efficient victim caches
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ICCD
2008
IEEE
117views Hardware» more  ICCD 2008»
14 years 3 months ago
Two dimensional highly associative level-two cache design
High associativity is important for level-two cache designs [9]. Implementing CAM-based Highly Associative Caches (CAM-HAC), however, is both costly in hardware and exhibits poor s...
Chuanjun Zhang, Bing Xue
GLOBECOM
2007
IEEE
14 years 18 days ago
Power Efficient IP Lookup with Supernode Caching
— In this paper, we propose a novel supernode caching scheme to reduce IP lookup latencies and energy consumption in network processors. In stead of using an expensive TCAM based...
Lu Peng, Wencheng Lu, Lide Duan
ICCD
2006
IEEE
138views Hardware» more  ICCD 2006»
14 years 3 months ago
Delay and Area Efficient First-level Cache Soft Error Detection and Correction
—Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but ar...
Karl Mohr, Lawrence Clark
DSD
2004
IEEE
132views Hardware» more  DSD 2004»
13 years 10 months ago
Dynamic Filter Cache for Low Power Instruction Memory Hierarchy
Filter cache(FC) is effective in achieving energy saving at the expense of some performance degradation. The energy savings, here, comes from repeated execution of tiny loops from...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
C3S2E
2009
ACM
13 years 10 months ago
The promise of solid state disks: increasing efficiency and reducing cost of DBMS processing
Most database systems (DBMSs) today are operating on servers equipped with magnetic disks. In our contribution, we want to motivate the use of two emerging and striking technologi...
Karsten Schmidt 0002, Yi Ou, Theo Härder