88 search results - page 5 / 18 » Reducing energy and delay using efficient victim caches |
107
click to vote
ISLPED
2010
ACM
14 years 7 months ago
2010
ACM
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
IPPS
1999
IEEE
15 years 1 months ago
1999
IEEE
In this paper we propose a simple extension to the I/O architecture of scalable multiprocessors that optimizes page swap-outs significantly. More specifically, we propose the use o...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract—Caches often employ write-back instead of writethrough, since write-back avoids unnecessary transfers for multiple writes to the same block. For several reasons, however...
ICCAD
2009
IEEE
14 years 7 months ago
2009
IEEE
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
On chip memories provide fast and energy efficient storage for code and data in comparison to caches or external memories. We present techniques and algorithms that allow for an au...