88 search results - page 8 / 18 » Reducing energy and delay using efficient victim caches |
ICCAD
2010
IEEE
14 years 7 months ago
2010
IEEE
3D stacked circuits reduce communication delay in multicore system-on-chips (SoCs) and enable heterogeneous integration of cores, memories, sensors, and RF devices. However, vertic...
DATE
2008
IEEE
14 years 11 months ago
2008
IEEE
We propose two crosstalk reducing coding schemes using ternary busses. In addition to low power consumption and reduced delay, our schemes offer other advantages over binary codin...
ISCA
2008
IEEE
14 years 9 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
ICS
2009
Tsinghua U.
15 years 2 months ago
2009
Tsinghua U.
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
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ICCD
2007
IEEE
15 years 6 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...