25 search results - page 5 / 5 » Reducing power consumption of instruction ROMs by exploiting... |
CASES
2005
ACM
13 years 8 months ago
2005
ACM
Code compression is a field where compression ratios between compiler-generated code and subsequent compressed code are highly dependent on decisions made at compile time. Most op...
IISWC
2009
IEEE
14 years 27 days ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
HPCA
2007
IEEE
14 years 6 months ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
MICRO
2008
IEEE
14 years 19 days ago
2008
IEEE
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
CF
2010
ACM
13 years 11 months ago
2010
ACM
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...