25 search results - page 1 / 5 » Reducing test time with processor reuse in network-on-chip b... |
SBCCI
2004
ACM
15 years 3 months ago
2004
ACM
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
WORDS
2003
IEEE
15 years 2 months ago
2003
IEEE
In the Komodo project a real-time Java system based on a multithreaded Java microcontroller has been developed. A main scheduling policy realized by hardware in the microcontroller...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper, we propose a new method for test access and test scheduling in NoC-based system. It relies on a progressive reuse of the network resources for transporting test dat...
ITC
1996
IEEE
15 years 1 months ago
1996
IEEE
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...