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» Reducing the Complexity of Defect Level Modeling Using the C...
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DATE
2000
IEEE
71views Hardware» more  DATE 2000»
15 years 5 months ago
Reducing the Complexity of Defect Level Modeling Using the Clustering Effect
José T. de Sousa, Vishwani D. Agrawal
94
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ATS
2003
IEEE
105views Hardware» more  ATS 2003»
15 years 6 months ago
Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method
Recent probabilistic test generation approaches have proven that detecting single stuck-at faults multiple times is effective at reducing the defective part level (DPL). Unfortuna...
Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. R...
105
Voted
ICPP
2009
IEEE
15 years 7 months ago
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
Yolanda Becerra, Vicenç Beltran, David Carr...
ITC
1998
IEEE
174views Hardware» more  ITC 1998»
15 years 4 months ago
High volume microprocessor test escapes, an analysis of defects our tests are missing
This paper explores defects found in a high volume microprocessor when shipping at a low defect level. A brief description of the manufacturing flow along with definition of DPM i...
Wayne M. Needham, Cheryl Prunty, Yeoh Eng Hong
108
Voted
ICSE
2008
IEEE-ACM
16 years 1 months ago
Predicting defects using network analysis on dependency graphs
In software development, resources for quality assurance are limited by time and by cost. In order to allocate resources effectively, managers need to rely on their experience bac...
Thomas Zimmermann, Nachiappan Nagappan