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ENTCS
2010
127views more  ENTCS 2010»
14 years 9 months ago
Combining Model Reductions
Molecular biological models usually suffer from a large combinatorial explosion. Indeed, proteins form complexes and modify each others, which leads to the formation of a huge num...
Ferdinanda Camporesi, Jérôme Feret, H...
DSD
2009
IEEE
83views Hardware» more  DSD 2009»
15 years 24 days ago
Streaming Reduction Circuit
—Reduction circuits are used to reduce rows of floating point values to single values. Binary floating point operators often have deep pipelines, which may cause hazards when m...
Marco Gerards, Jan Kuper, André B. J. Kokke...
67
Voted
ICC
2007
IEEE
15 years 3 months ago
Low-Complexity, Low-Memory EMS Algorithm for Non-Binary LDPC Codes
— In this paper, we propose a new implementation of the EMS decoder for non binary LDPC codes presented in [7]. A particularity of the new algorithm is that it takes into account...
Adrian Voicila, David Declercq, François Ve...
FGR
2008
IEEE
134views Biometrics» more  FGR 2008»
15 years 4 months ago
HMM parameter reduction for practical gesture recognition
We examine in detail some properties of gesture recognition models which utilize a reduced number of parameters and lower algorithmic complexity compared to traditional hidden Mar...
Stjepan Rajko, Gang Qian
99
Voted
ASPDAC
1995
ACM
108views Hardware» more  ASPDAC 1995»
15 years 1 months ago
Transistor reordering rules for power reduction in CMOS gates
— The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power cons...
Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang