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CDES
2006
98views Hardware» more  CDES 2006»
15 years 1 months ago
Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer
Recently, several loop buffer designs have been proposed to reduce instruction fetch energy due to size and location advantage of loop buffer. Nevertheless, on design complexity di...
Bin-Hua Tein, I-Wei Wu, Chung-Ping Chung
DLT
2003
15 years 1 months ago
NFA Reduction Algorithms by Means of Regular Inequalities
We present different techniques for reducing the number of states and transitions in nondeterministic automata. These techniques are based on the two preorders over the set of st...
Jean-Marc Champarnaud, Fabien Coulon
SIGCOMM
2012
ACM
13 years 2 months ago
DeTail: reducing the flow completion time tail in datacenter networks
Web applications have now become so sophisticated that rendering a typical page may require hundreds of intra-datacenter flows. At the same time, web sites must meet strict page ...
David Zats, Tathagata Das, Prashanth Mohan, Dhruba...
CVPR
2009
IEEE
16 years 6 months ago
Reducing JointBoost-Based Multiclass Classification to Proximity Search
Boosted one-versus-all (OVA) classifiers are commonly used in multiclass problems, such as generic object recognition, biometrics-based identification, or gesture recognition. Join...
Alexandra Stefan (University of Texas at Arlington...
ICNP
2006
IEEE
15 years 5 months ago
Reducing Congestion Effects in Wireless Networks by Multipath Routing
Abstract—We propose a solution to improve fairness and increase throughput in wireless networks with location information. Our approach consists of a multipath routing protocol, ...
Lucian Popa 0002, Costin Raiciu, Ion Stoica, David...