6568 search results - page 26 / 1314 » Reducing the Complexity of Reductions |
ICCAD
2010
IEEE
14 years 9 months ago
2010
IEEE
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
100
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EUROCOLT
1995
Springer
15 years 3 months ago
1995
Springer
Limiting identification of r.e. indexes for r.e. languages (from a presentation of elements of the language) and limiting identification of programs for computable functions (fr...
DATE
2010
IEEE
15 years 5 months ago
2010
IEEE
—1 In this paper we present a stochastic model order reduction technique for interconnect extraction in the presence of process variabilities, i.e. variation-aware extraction. It...
ASPDAC
2008
ACM
15 years 1 months ago
2008
ACM
In this paper, we propose a new model order reduction approach for large interconnect circuits using hierarchical decomposition and Krylov subspace projection-based model order re...
103
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CF
2005
ACM
15 years 1 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...