The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
In this paper we propose a novel parameterized interconnect order reduction algorithm, CORE, to efficiently capture both inter-die and intra-die variations. CORE applies a two-ste...
— Selected mapping (SLM) is a well-known method for reducing the peak-to-average power ratio (PAPR) in orthogonal frequency-division multiplexing (OFDM) systems. The main drawbac...
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already...
The ranking problem appears in many areas of study such as customer rating, social science, economics, and information retrieval. Ranking can be formulated as a classification pro...