6568 search results - page 82 / 1314 » Reducing the Complexity of Reductions |
143
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FPL
2010
Springer
15 years 4 months ago
2010
Springer
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the to...
159
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HICSS
2005
IEEE
15 years 11 months ago
2005
IEEE
Peer-to-Peer protocols and applications have drawn much attention. Freenet is a groundbreaking Peer-to-Peer system that protects the anonymity of information producers, consumers,...
139
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DFT
2002
IEEE
15 years 11 months ago
2002
IEEE
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
148
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ISCA
1997
IEEE
15 years 9 months ago
1997
IEEE
Deeply pipelined, superscalar processors require accurate branch prediction to achieve high performance. Two-level branch predictors have been shown to achieve high prediction acc...
131
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VLSID
2004
IEEE
16 years 6 months ago
2004
IEEE
Reduction of worst-case delay and delay uncertainty due to capacitive coupling is a still unsolved problem in physical design. We describe a routing only layout solution - swizzli...