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» Reducing the Complexity of Reductions
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162
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DFT
2009
IEEE
106views VLSI» more  DFT 2009»
16 years 27 days ago
Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points
Recently, a new test point insertion method for pseudo-random built-in self-test (BIST) was proposed in [Yang 09] which tries to use functional flip-flops to drive control test po...
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
EVOW
2007
Springer
16 years 9 days ago
Reducing the Size of Traveling Salesman Problem Instances by Fixing Edges
Abstract. The Traveling Salesman Problem (TSP) is a well-known NPhard combinatorial optimization problem, for which a large variety of evolutionary algorithms are known. However, t...
Thomas Fischer, Peter Merz
151
Voted
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
15 years 11 months ago
Instruction packing: reducing power and delay of the dynamic scheduling logic
The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for...
Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghos...
ITC
2003
IEEE
214views Hardware» more  ITC 2003»
15 years 11 months ago
ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume
This paper presents an approach for reducing the test data volume that has to be stored in ATE vector memory for IC manufacturing testing. We exploit the capabilities of present A...
Harald P. E. Vranken, Friedrich Hapke, Soenke Rogg...
ISSS
1999
IEEE
149views Hardware» more  ISSS 1999»
15 years 10 months ago
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
Synchronous Dataflow, a subset of dataflow, has proven to be a good match for specifying DSP programs. Because of the limited amount of memory in embedded DSPs, a key problem duri...
Praveen K. Murthy, Shuvra S. Bhattacharyya