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DATE
1998
IEEE
110views Hardware» more  DATE 1998»
15 years 10 months ago
Scheduling and Module Assignment for Reducing Bist Resources
Built-in self-test BIST techniques modify functional hardware to give a data path the capability to test itself. The modi cation of data path registers into registers BIST resourc...
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breue...
VTS
1997
IEEE
86views Hardware» more  VTS 1997»
15 years 10 months ago
Methods to reduce test application time for accumulator-based self-test
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...
Albrecht P. Stroele, Frank Mayer
CEC
2003
IEEE
15 years 9 months ago
Genome-physics interaction as a new concept to reduce the number of genetic parameters in artificial evolution
This paper reports on investigations on the possible advantage of the coupling between genomes and physics of cells in artificial evolution. The idea is simple: evolution can rely ...
Peter Eggenberger Hotz
AAAI
2008
15 years 8 months ago
AnalogySpace: Reducing the Dimensionality of Common Sense Knowledge
We are interested in the problem of reasoning over very large common sense knowledge bases. When such a knowledge base contains noisy and subjective data, it is important to have ...
Robert Speer, Catherine Havasi, Henry Lieberman
DSN
2008
IEEE
15 years 8 months ago
An accurate flip-flop selection technique for reducing logic SER
The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In...
Eric L. Hill, Mikko H. Lipasti, Kewal K. Saluja