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» Reducing the Complexity of Reductions
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180
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ICASSP
2009
IEEE
16 years 1 months ago
Reducing F0 Frame Error of F0 tracking algorithms under noisy conditions with an unvoiced/voiced classification frontend
In this paper, we propose an F0 Frame Error (FFE) metric which combines Gross Pitch Error (GPE) and Voicing Decision Error (VDE) to objectively evaluate the performance of fundame...
Wei Chu, Abeer Alwan
151
Voted
ARITH
2005
IEEE
15 years 12 months ago
Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition
In this paper we propose an architecture for the computation of the double—precision floating—point multiply—add fused (MAF) operation A + (B × C) that permits to compute ...
Javier D. Bruguera, Tomás Lang
ITC
2003
IEEE
141views Hardware» more  ITC 2003»
15 years 11 months ago
Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...
Kartik Mohanram, Nur A. Touba
ICC
2000
IEEE
15 years 10 months ago
Reduced-State BCJR-Type Algorithms
—In this paper, we propose a technique to reduce the number of trellis states in BCJR-type algorithms, i.e., algorithms with a structure similar to that of the well-known algorit...
Giulio Colavolpe, Gian Luigi Ferrari, Riccardo Rah...
IDA
2000
Springer
15 years 6 months ago
Reducing redundancy in characteristic rule discovery by using integer programming techniques
The discovery of characteristic rules is a well-known data mining task and has lead to several successful applications. However, because of the descriptive nature of characteristic...
Tom Brijs, Koen Vanhoof, Geert Wets