Sciweavers

387 search results - page 3 / 78
» Reducing the Costs of Bounded-Exhaustive Testing
Sort
View
DATE
2008
IEEE
112views Hardware» more  DATE 2008»
15 years 4 months ago
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
Paolo Bernardi, Matteo Sonza Reorda
95
Voted
DFT
2004
IEEE
101views VLSI» more  DFT 2004»
15 years 1 months ago
Designs for Reducing Test Time of Distributed Small Embedded SRAMs
This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improv...
Baosheng Wang, Yuejian Wu, André Ivanov
PC
2010
111views Management» more  PC 2010»
14 years 8 months ago
Reducing complexity in tree-like computer interconnection networks
The fat-tree is one of the topologies most widely used to build high-performance parallel computers. However, they are expensive and difficult to build. In this paper we propose t...
Javier Navaridas, José Miguel-Alonso, Franc...
STVR
2002
88views more  STVR 2002»
14 years 9 months ago
Empirical studies of test-suite reduction
Test-suite reduction techniques attempt to reduce the costs of saving and reusing test cases during software maintenance by eliminating redundant test cases from test suites. A po...
Gregg Rothermel, Mary Jean Harrold, Jeffery von Ro...
ACTAC
1999
81views more  ACTAC 1999»
14 years 9 months ago
Test Suite Reduction in Conformance Testing
Conformance testing is based on a test suite. Standardization committees release standard test suites, which consist of hundreds of test cases. The main problem of conformance tes...
Tibor Csöndes, Sarolta Dibuz, Balázs K...