221 search results - page 12 / 45 » Reducing the Interconnection Network Cost of Chip Multiproce... |
IEEEPACT
2002
IEEE
15 years 2 months ago
2002
IEEE
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
IEEEPACT
2008
IEEE
15 years 3 months ago
2008
IEEE
The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power...
ISCA
2010
IEEE
15 years 2 months ago
2010
IEEE
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
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CAL
2008
14 years 9 months ago
2008
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
INFOCOM
2012
IEEE
12 years 12 months ago
2012
IEEE
—Economic forces behind the Internet evolution have diversified the types of ISP (Internet Service Provider) interconnections. In particular, settlement-free peering and paid pe...