221 search results - page 20 / 45 » Reducing the Interconnection Network Cost of Chip Multiproce... |
SLIP
2006
ACM
15 years 5 months ago
2006
ACM
A fundamental difference between ASICs and FPGAs is that wires in ASICs are designed such that it matches the requirements of a particular design. Wire parameters such as: length...
85
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DATE
2010
IEEE
14 years 10 months ago
2010
IEEE
Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its to...
ICCAD
2008
IEEE
15 years 8 months ago
2008
IEEE
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...
112
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CODES
2007
IEEE
15 years 6 months ago
2007
IEEE
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
ISCA
2008
IEEE
14 years 11 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...