723 search results - page 58 / 145 » Reducing the complexity of the issue logic |
ICNP
2009
IEEE
15 years 6 months ago
2009
IEEE
—Routing protocols are implemented in the form of software running on a general-purpose microprocessor. However, conventional software-based router architectures face significan...
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ISQED
2011
IEEE
14 years 3 months ago
2011
IEEE
Due to the dramatic increase in design complexity, verifying the functional correctness of a circuit is becoming more difficult. Therefore, bugs may escape all verification effo...
DDECS
2007
IEEE
15 years 6 months ago
2007
IEEE
— To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scal...
CODES
2002
IEEE
15 years 4 months ago
2002
IEEE
This paper describes the formal verification of the recently introduced Dual Transition Petri Net (DTPN) models [12], using model checking techniques. The methodology presented a...
MEDINFO
2007
15 years 1 months ago
2007
After a critical review of the present architecture of SNOMED CT, addressing both logical and ontological issues, we present a roadmap towards an overall improvement of this termi...