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» Reduction Transformations in ORM
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DATE
2010
IEEE
124views Hardware» more  DATE 2010»
15 years 4 months ago
Control network generator for latency insensitive designs
—Creating latency insensitive or asynchronous designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations h...
Eliyah Kilada, Kenneth S. Stevens
GI
2009
Springer
15 years 4 months ago
Reasoning about Contextual Equivalence: From Untyped to Polymorphically Typed Calculi
: This paper describes a syntactical method for contextual equivalence in polymorphically typed lambda-calculi. Our specific calculus has letrec as cyclic let, data constructors, ...
David Sabel, Manfred Schmidt-Schauß, Frederi...
ICCAD
2000
IEEE
113views Hardware» more  ICCAD 2000»
15 years 4 months ago
Don't Cares and Multi-Valued Logic Network Minimization
We address optimizing multi-valued (MV) logic functions in a multi-level combinational logic network. Each node in the network, called an MV-node, has multi-valued inputs and sing...
Yunjian Jiang, Robert K. Brayton
ICCAD
1996
IEEE
121views Hardware» more  ICCAD 1996»
15 years 4 months ago
Identification of unsettable flip-flops for partial scan and faster ATPG
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs
FASE
2004
Springer
15 years 3 months ago
Translating Software Designs for Model Checking
Abstract. This paper presents a systematic consideration of the major issues involved in translation of executable design level software specification languages to directly model-c...
Fei Xie, Vladimir Levin, Robert P. Kurshan, James ...