Our goal is to transform a low-level circuit design into a more representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equiv...
In this paper we give a new run–time technique for finding an optimal parallel execution schedule for a partially parallel loop, i.e., a loop whose parallelization requires syn...
Lawrence Rauchwerger, Nancy M. Amato, David A. Pad...
In recent years there have been several approaches for the automatic derivation of labels from an unlabeled reactive system. This can be done in such a way that the resulting bisim...
There are numerous cadastral maps generated by past land surveying. For effective and efficient use of these maps, we have to assemble the set of maps to make them superimposable ...
Embedded systems often have limited amounts of available memory, thus encouraging the development of compact programs. This paper presents a link-time program compactor for the emb...
Matias Madou, Bjorn De Sutter, Bruno De Bus, Ludo ...