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ICCAD
1997
IEEE
97views Hardware» more  ICCAD 1997»
15 years 4 months ago
Low power logic synthesis for XOR based circuits
An abundance of research e orts in low power logic synthesis have so far been focused on and or or nand nor based logic. A typical approach is to rst generate an initial multi-lev...
Unni Narayanan, C. L. Liu
DAC
1997
ACM
15 years 3 months ago
A Graph-Based Synthesis Algorithm for AND/XOR Networks
In this paper, we introduce a Shared Multiple Rooted XORbased Decomposition Diagram XORDD to represent functions with multiple outputs. Based on the XORDD representation, we dev...
Yibin Ye, Kaushik Roy
76
Voted
ASPDAC
2007
ACM
124views Hardware» more  ASPDAC 2007»
15 years 3 months ago
BddCut: Towards Scalable Symbolic Cut Enumeration
While the covering algorithm has been perfected recently by the iterative approaches, such as DAOmap and IMap, its application has been limited to technology mapping. The main fact...
Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
ASYNC
2004
IEEE
102views Hardware» more  ASYNC 2004»
15 years 3 months ago
Non-Uniform Access Asynchronous Register Files
Register files of microprocessors have often been cited as performance bottlenecks and significant consumers of energy. The robust and modular nature of quasi-delay insensitive (Q...
David Fang, Rajit Manohar
CGO
2004
IEEE
15 years 3 months ago
Exploring Code Cache Eviction Granularities in Dynamic Optimization Systems
Dynamic optimization systems store optimized or translated code in a software-managed code cache in order to maximize reuse of transformed code. Code caches store superblocks that...
Kim M. Hazelwood, James E. Smith