39 search results - page 8 / 8 » Register File Architecture Optimization in a Coarse-Grained ... |
114
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TVLSI
2010
14 years 4 months ago
2010
This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband processing in wireless terminals. It builds on our earlier architecture--Signal processi...
114
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FPGA
2010
ACM
14 years 9 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
62
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DAC
2009
ACM
15 years 10 months ago
2009
ACM
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...
104
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TPDS
2008
14 years 9 months ago
2008
This paper presents the Mitosis framework, which is a combined hardware-software approach to speculative multithreading, even in the presence of frequent dependences among threads....