27 search results - page 1 / 6 » Register allocation with instruction scheduling for VLIW-arc... |
CASES
2001
ACM
13 years 10 months ago
2001
ACM
In this paper we describe a design exploration methodology for clustered VLIW architectures. The central idea of this work is a set of three techniques aimed at reducing the cost ...
LCTRTS
2007
Springer
14 years 19 days ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
DATE
2005
IEEE
14 years 3 days ago
2005
IEEE
With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism...
DATE
2006
IEEE
14 years 17 days ago
2006
IEEE
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
PCS
2010
13 years 1 months ago
2010
