12 search results - page 1 / 3 » Register binding and port assignment for multiplexer optimiz... |
59
Voted
ASPDAC
2004
ACM
15 years 3 months ago
2004
ACM
- Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult pro...
TVLSI
2010
14 years 4 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
– With the rapid increase of design complexity and the decrease of device features in nano-scale technologies, interconnection optimization in digital systems becomes more and mo...
DAC
1995
ACM
15 years 1 months ago
1995
ACM
This paper describes a technique for calculating the switching activity of a set of registers shared by di erent data values. Based on the assumption that the joint pdf (probabili...
73
Voted
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based ...