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ASAP
2003
IEEE
107views Hardware» more  ASAP 2003»
15 years 5 months ago
Energy Aware Register File Implementation through Instruction Predecode
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
José L. Ayala, Marisa Luisa López-Va...
ARVLSI
1999
IEEE
112views VLSI» more  ARVLSI 1999»
15 years 4 months ago
Architectural Considerations for Application-Specific Counterflow Pipelines
Application-specific processor design is a promising approach for meeting the performance and cost goals of a system. Application-specific processors are especially promising for ...
Bruce R. Childers, Jack W. Davidson
LCTRTS
2009
Springer
15 years 6 months ago
A compiler optimization to reduce soft errors in register files
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
Jongeun Lee, Aviral Shrivastava
VLSID
2004
IEEE
107views VLSI» more  VLSID 2004»
16 years 6 days ago
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
Sourabh Saluja, Anshul Kumar
FCCM
2003
IEEE
135views VLSI» more  FCCM 2003»
15 years 5 months ago
Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable
Hybrid architectures, which are composed of a conventional processor closely coupled with reconfigurable logic, seem to combine the advantages of both types of hardware. They pres...
Benjamin A. Levine, Herman Schmit