199 search results - page 18 / 40 » Register pointer architecture for efficient embedded process... |
IJCSA
2008
14 years 12 months ago
2008
Vector extensions for general purpose processors are an efficient feature to address the growing performance demand of multimedia and computer vision applications. Embedded proces...
CATA
2004
15 years 1 months ago
2004
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the domi...
ISCAS
2008
IEEE
15 years 6 months ago
2008
IEEE
—Software-based self-test (SBST) is a promising new technology for at-speed testing of embedded processors in SoC systems. This paper introduces an effective and efficient new ho...
130
click to vote
TVLSI
2008
2008
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
14 years 11 months ago
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...