199 search results - page 34 / 40 » Register pointer architecture for efficient embedded process... |
101
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HPCA
2003
IEEE
16 years 6 days ago
2003
IEEE
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
DATE
2004
IEEE
15 years 3 months ago
2004
IEEE
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
CF
2006
ACM
15 years 3 months ago
2006
ACM
This paper presents our experience mapping OpenMP parallel programming model to the IBM Cyclops-64 (C64) architecture. The C64 employs a many-core-on-a-chip design that integrates...
EMSOFT
2006
Springer
15 years 3 months ago
2006
Springer
In-situ reconfiguration of software is indispensable in embedded networked sensing systems. It is required for re-tasking a deployed network, fixing bugs, introducing new features...
110
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ANCS
2007
ACM
15 years 3 months ago
2007
ACM
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...