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VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
16 years 6 days ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
FPGA
2008
ACM
129views FPGA» more  FPGA 2008»
15 years 1 months ago
Efficient ASIP design for configurable processors with fine-grained resource sharing
Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. ...
Quang Dinh, Deming Chen, Martin D. F. Wong
VLSID
2002
IEEE
142views VLSI» more  VLSID 2002»
16 years 6 days ago
Address Code and Arithmetic Optimizations for Embedded Systems
An important class of problems used widely in both the embedded systems and scientific domains perform memory intensive computations on large data sets. These data sets get to be ...
J. Ramanujam, Satish Krishnamurthy, Jinpyo Hong, M...
FPL
2010
Springer
111views Hardware» more  FPL 2010»
14 years 9 months ago
Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays
Abstract--Efficient storage in spatial processors is increasingly important as such devices get larger and support more concurrent operations. Unlike sequential processors that rel...
Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebe...
ASPDAC
2008
ACM
89views Hardware» more  ASPDAC 2008»
15 years 1 months ago
Load scheduling: Reducing pressure on distributed register files for free
In this paper we describe load scheduling, a novel method that balances load among register files by residual resources. Load scheduling can reduce register pressure for clustered...
Mei Wen, Nan Wu, Maolin Guan, Chunyuan Zhang