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ICCD
2004
IEEE
101views Hardware» more  ICCD 2004»
15 years 8 months ago
Increasing Processor Performance Through Early Register Release
Modern superscalar microprocessors need sizable register files to support large number of in-flight instructions for exploiting ILP. An alternative to building large register file...
Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kan...
SCOPES
2007
Springer
15 years 6 months ago
Efficient event-driven simulation of parallel processor architectures
Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, ...
FPGA
2005
ACM
107views FPGA» more  FPGA 2005»
15 years 5 months ago
Instruction set extension with shadow registers for configurable processors
Configurable processors are becoming increasingly popular for modern embedded systems (especially for the field-programmable system-on-a-chip). While steady progress has been made...
Jason Cong, Yiping Fan, Guoling Han, Ashok Jaganna...
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
15 years 5 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...
DAC
2005
ACM
16 years 24 days ago
Towards scalable flow and context sensitive pointer analysis
Pointer analysis, a classic problem in software program analysis, has emerged as an important problem to solve in design automation, at a time when complex designs, specified in t...
Jianwen Zhu