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DAC
2006
ACM
16 years 24 days ago
Rapid and low-cost context-switch through embedded processor customization for real-time and control applications
In this paper, we present a methodology for low-cost and rapid context switch for multithreaded embedded processors with realtime guarantees. Context-switch, which involves saving...
Xiangrong Zhou, Peter Petrov
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
15 years 6 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky
CGO
2010
IEEE
15 years 6 months ago
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bi
For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM T...
Tobias J. K. Edler von Koch, Igor Böhm, Bj&ou...
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
15 years 6 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
ACSAC
2003
IEEE
15 years 3 months ago
Defending Embedded Systems Against Buffer Overflow via Hardware/Software
Buffer overflow attacks have been causing serious security problems for decades. With more embedded systems networked, it becomes an important research problem to defend embedded ...
Zili Shao, Qingfeng Zhuge, Yi He, Edwin Hsing-Mean...